----------------------------------------------------------------
-- Test Bench for D flip-flop
----------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity tb_reg1bit is		-- entity declaration
end tb_reg1bit;

----------------------------------------------------------------

architecture TB of tb_reg1bit is

    signal T_data: 	std_logic;
    signal T_clock:	std_logic;
    signal T_rw:	std_logic;
    signal T_e:		std_logic;
	
    component cmp_reg1bit
    port(	data:		inout std_logic;
    		rw:		in std_logic;
    		e:		in std_logic;
    		clock:		in std_logic
    );
    end component;
		
begin

    U_DFF: cmp_reg1bit port map (T_data, T_rw, T_e, T_clock);

    -- concurrent process to offer clock signal	
    process
    begin
	T_clock <= '0';
	wait for 5 ns;
	T_clock <= '1';
	wait for 5 ns;
    end process;
	
    process

	variable err_cnt: integer := 0; 

    begin
		
	-- case 1 -- Escribo 1 en la memoria, pero est� deshabilitada
	T_data <= '1';
	T_rw <= '0';
	T_e <= '0';
	wait for 12 ns;		 
	assert (T_data='1') report "Error1!" severity error;
	if (T_data/='1') then
	    err_cnt := err_cnt + 1;
	end if;

	-- case 2 -- Escribo 1 en la memoria, habilitada 
	T_data <= '1';
	T_rw <= '1';
	T_e <=  '1';	 
	wait for 12 ns;
	assert (T_data='1') report "Error2!" severity error;
	if (T_data/='1') then
	    err_cnt := err_cnt + 1;
	end if;

	-- case 3 -- Escribo 0 en la memoria, deshabilitada  
	T_data <= '0';
	T_rw <= '1';
	T_e <=  '0'; 
	wait for 12 ns;
	assert (T_data='0') report "Error3!" severity error;
	if (T_data/='0') then
	    err_cnt := err_cnt + 1;
	end if;
		
	-- case 4 -- Leo la memoria
	T_data <= 'Z';
	T_rw <= '0';
	T_e <=  '1';	 
	wait for 12 ns;
	assert (T_data='1') report "Error4!" severity error;
	if (T_data/='1') then
	    err_cnt := err_cnt + 1;
	end if;

	wait;

    end process;

end TB;

-----------------------------------------------------------------
configuration CFG_TB of tb_reg1bit is
	for TB
	end for;
end CFG_TB;
-----------------------------------------------------------------

